Vipin Kizheppatt is an Assitant Professor with MEC in the Computer Science and Engineering and Electrical and Electronic Engineering disciplines. He graduated from Rajiv Gandhi Institute of Technology, under Mahatma Gandhi University, Kottayam in 2007 with Distinction in Electronics and Communication Engineering. From 2007 to 2010, he worked as an FPGA design and development engineer at Processor Systems India Pvt. Ltd in Bangalore. In 2010 he joined School of Computer Engineering, Nanyang Technological University under the Division of Hardware and Embedded Systems to pursue his PhD. He completed his PhD in 2015 January
His research is mainly focused on adaptive systems with particular emphasis on design automation of hardware supported adaptive systems based on partial reconfiguration of field programmable gate arrays (FPGAs).
Contact: Vipin.Kizheppatt[at]mechyd.ac.in 040-67135148
Vipin's area of research is broadly focused on embedded systems, reconfigurable computing based on field programmable gate arrays (FPGAs), and adaptive systems and their practical engineering applications.
This work is mainly concentrated on FPGA reconfiguration and its applications. A design flow is developed, based on high-level application descriptions, that will allow adaptive systems to be designed and implemented on FPGAs, with minimal low-level hardware knowledge. This research aims to build on prior work in the area, but to propose a much more robust and general solution to building adaptive systems, which is accessible to domain experts. The aim of this research project is to design the infrastructure and tools necessary to enable the high-level design of adaptive hardware systems, with the aim of making the process accessible to those who are not hardware or FPGA experts. As part of the project, example applications in cognitive radio and automotive applications will be demonstrated.
Partial reconfiguration (PR) involves selectively modifying only portions of an FPGA while the remaining portions continue to execute without interruption. Although proposed more than two decades before and available in commercial FPGAs for more than a decade, its adoption in mainstream FPGA system design remains underwhelming. The inital research goal is to understand the challenges preventing the wide spread acceptance of this technique. In the later stage we will try to propose techniques, methodologies and solutions for adopting PR in system development.
This involves some real engineering work. The aim is to develop systems which aid in my mainstream research work along with helping to keep uptodate with industrial trends. Industry leaders such as Xilinx and Altera are releasing new hardware and software in such a fast-pace that pure theoretical research works become quickly obsolete. Presently the favourite development platform is Xilinx's latest Zynq APSoC. Multiple open-source IP cores are released to make this platform more attractive for researchers and developers. More details in my git repository.
Below is a list of my publications. Copyright and all rights therein are retained by authors or by other copyright holders.
Teaching assistant at NTU for
Design Engineer (Hardware), Processor Systems India Pvt. Ltd (ProcSys), Bangalore, 2007-2009 Associate Senior Engineer, Processor Systems India Pvt. Ltd (ProcSys), Bangalore, 2009-2010