Pooran Singh

Dr. Pooran Singh is an Assistant Professor in the Electrical and Electronics Engineering Department at Mahindra University École Centrale School of Engineering. Dr. Pooran did his Ph.D. from the Department of Electrical Engineering, IIT Indore.

Prior to joining MU, he was an Analog Design Engineer (SRAM Design) at Intel Microelectronics, Penang, Malaysia, his primary work included designing SRAM circuits, Pre-layout SRAM design and analysis of its various design parameters i.e. read margin/write margin, critical path, read/write performance, dynamic and leakage power at different PVT values for Intel’s 7nm and 10nm FPGAs.

• Education
  • 2018    Doctor of Philosophy (VLSI Design), Department of Electrical Engineering, Indian Institute of Technology Indore (IIT Indore), M. P., India
    Thesis Title: Ultra low power, High-stability robust SRAM design for FPGA, Image Processing, and IoT Applications
  • 2010    Master of Technology (VLSI Design), Department of Electrical Engineering, ABV-Indian Institute of Information Technology & Management Gwalior, M. P., India 
  • 2007    Bachelor of Engineering, Electronics & Communication (ECE), RGPV University, Bhopal (M. P.) 
• Research

  Research Interests:

  •    Ultra-low power SRAM design and architecture
  •    High-performance robust memory design for AI and smart devices
  •    Digital ASIC/SoC design for IoT, AI and smart devices

• Awards
  1. 10/2014 - 07/2015 Fulbright-Nehru Doctoral Research Fellowship, USIEF, Georgia Tech, Atlanta, Georgia, USA
  2. 2014 - 2015 Patel Fellowship, Institute of International Education (IIE), USA
  3. 01/2010-10/2017 PhD Research Fellowship, MHRD, Govt. of India
  4. 07/2008-05/2010 GATE (Graduate Aptitude Test in Engineering) Fellowship
• Publications

  Citation:

  Google Citation: 84, h-index: 6, i-10 index: 2

  Publications Summary:

  Journals: 12, Conferences: 07, Patents: 01 (Filed)

  List of Selected Publications:

  • Pooran Singh and S. K. Vishvakarma, “Low leakage-high stability differential positive feedback controlled 10T (DPFC10T) SRAM Cell,” Application No. 201621038192 (Filed patent on 8th Nov. 2016).
  • Bhupendra Singh Reniwal, Vikas Vijayvargiya, Pooran Singh, Nandkishor Yadav, Santosh Kumar Vishvakarma and Devesh Dwivedi, "An Auto Calibrated Sense Amplifier with Offset Prediction Approach for Energy Efficient SRAM, "Circuits, Systems & Signal Processing (CSSP), Springer, Aug. 2018 [PDF]
  • Vishal Sharma, Maisagalla Gopal, Pooran Singh, Santosh Kumar Vishvakarma and Shailesh Singh Chouhan, “A Robust, Ultra Low-Power, Data-Dependent-Power-Supplied 11T SRAM Cell with Expanded Read/Write Stabilities for Internet-of-Things Applications,” Analog Integrated Circuits and Signal Processing, Springer, pp 1-16, Aug, 2018. [PDF]
  • Pooran Singh and Santosh Kumar Vishvakarma, "Ultra Low Power-High Stability, Positive Feedback Controlled (PFC) 10T SRAM cell for Lookup Table (LUT) Design, "Integration, the VLSI Journal, Elsevier, vol. 62, pp 1-13, June 2018 [PDF]
  • Vishal Sharma, Maisagalla Gopal, Pooran Singh, and Santosh Kumar Vishvakarma, “A 220 mV Robust Read-Decoupled Partial Feedback Cutting based Low-Leakage 9T SRAM for Internet of Things (IoT) Applications,” International Journal of Electronics and Communications, Elsevier, vol. 87, pp. 144-157, April 2018. [PDF]
  • Pooran Singh and Santosh Kumar Vishvakarma, “Ultra low power process tolerant 10T (PT10T) SRAM with improved read/write ability for internet of things (IoT) applications," Journal of Low Power Electronics and Applications, vol. 7, no. 3, 24, pp. 1-22, Sept. 2017 [PDF]
  • Pooran Singh and Santosh Kumar Vishvakarma, "Ultra-Low Power High Stability 8T SRAM for Application in Object Tracking System", IEEE Access, Vol. 6, pp. 2279 - 2290, 2018.
  • Pooran Singh and Santosh Kumar Vishvakarma “Low Complexity-Low Power Object Tracking Using Dynamic Quad-tree Pixelation and Macro-block Resizing,” Pattern Recognition and Image Analysis, Springer, vol 27, issue 4, pp 731-739, Oct 2017. [PDF]
  • Pooran Singh, B. S. Reniwal, V. Vijayvargiya, Vishal Sharma and Santosh Kumar Vishvakarma," Dynamic Feedback-Controlled Static Random Access Memory for Low Power Applications", Journal of Low Power Electronics, ASP, Vol. 13, No. 1, pp. 47-59 (13), March 2017, ASP, USA. [PDF]
  • Pooran Singh and S. K. Vishvakarma, “Differential dynamic feedback controlled 10T SRAM for ultra-low power applications,” IEEE TC-VLSI Circuit and Systems Letter, vol. 3, no.1, pp. 6-12, Feb. 2017. 
  • Pooran Singh, B. S. Reniwal, V. Vijayvargiya, V. Sharma and S. K. Vishvakarma, “A 9T SRAM for ultra-low power applications,” 30th IEEE International Conference on VLSI Design and 16th International Conference on Embedded Systems, 7th -11th Jan. 2017, Hyderabad, India.
  • B. Reniwal, Pooran Singh, V. Vijayvargiya and S. K. Vishvakarma, “A new sense amplifier design with improved input referred offset characteristics for energy-efficient SRAM,” 30th IEEE International Conference on VLSI Design and 16th International Conference on Embedded Systems, 7th -11th Jan. 2017, Hyderabad, India.   
  • B. S. Reniwal, V. Vijayvargiya, Pooran Singh, S. K. Vishvakarma and D. Dwivedi, “Dataline isolated differential current feed/mode sense amplifier for small Icell SRAM using FinFET,” IEEE 25th Great Lakes Symposium on VLSI (GLSVLSI), 20th-22nd May 2015, Pittsburgh, PA, USA.
• Experience
  1. 03/2020 - Present     Assistant Professor, Electrical and Electronics Engineering, Mahindra University, Hyderabad, Telangana, India
  2. 11/2017 - 02/2020    Analog Design Engineer (SRAM Design), Intel Corporation, Penang, Malaysia
  3. 01/2012 - 10/2017    Teaching Assistant, IIT Indore, M. P., India              
  4. 10/2010 - 08/2011    Electronics Engineer, Baharat Electronics Ltd, Pune, MH, India